1. Field of the Invention
The present invention relates generally to a method of generating optimum skew corners for a compact device model, and more particularly pertains to method of generating a fast or slow skew corner model, or a fast-NFET, slow-PFET skew corner model, in which each of the parameters of compact device model is fixed to a particular value within its process distribution. A model parameter's values are set so that the model will reproduce the fast or slow corner results of several circuits performance targets, and wherein each model parameter's value in the skew corner library is within the tolerance range of that model parameter.
2. Discussion of the Prior Art
A compact device model in the semiconductor industry includes one or more of the following items: an FET device model (BSIM3, BSIM4, BSIMPD, Gummel-Poon, VBIC, etc.), models on passive devices (resistors, capacitors, inductors, etc.), and interconnect models. The compact model in the semiconductor industry plays an important role in linking a semiconductor device/chip manufacturer with circuit design companies or design teams. Circuit designers use a compact device model in a circuit simulator, such as IBM'S AS/X simulator, PowerSpice simulator, vendor's HSPICE simulator, SmartSpice simulator, Spectre simulator, etc. A typical compact model contains both nominal values of various model parameters as well as their standard deviations (i.e., 1-σ tolerance).
For an FET model, typical model parameters include TOX (oxide thickness), ΔL (difference between FET drawn design length and actual length), ΔW (difference between FET drawn design width and actual width), VT (threshold voltage), mobility, Cj (junction capacitance), etc. For a passive device such as a resistor, typical model parameters include sheet resistance of the resistor, its temperature coefficients, and the resistor's length and width, etc. For an interconnect model, typical model parameters include wire length, wire width, wire thickness, wire-to-wire space in the same metal level, vertical distance to a metal level above, and the vertical distance to a metal level below or to a substrate/N-well/diffusion region below it, etc.
With such nominal and tolerance values of model parameters, a circuit designer can do Monte Carlo simulations to obtain both nominal performance of a circuit and n-σ (e.g., 1-σ, 3-σ, or 6-σ, etc.) worst-case performance or n-σ best-case performance of the circuit. However, a practical limitation with the Monte Carlo simulation method is the huge CPU time required. The reason is that a single circuit simulation may take hours of intensive CPU time, and many times of circuit simulation are required to obtain a meaningful statistical sample.
To save circuit simulation time, for circuit designers, it is often desirable to have a worst-case (best-case) skew-corner library for simulating the worst-case (best-case) behavior of the circuit. This saves a lot of circuit simulation time, since only a single simulation is needed to obtain the worst-case circuit performance number with the use of a worst-case skew-corner library.
A commonly used skew corner method is to shift all model parameters together, i.e., shift them in the same percentage with respect to each model parameter's standard deviation. As explained hereinbelow, such a method usually does not produce an optimum skew corner for a single performance target. For multiple performance targets, such a single skew corner typically will not reproduce the worst case (or best case) performance results of several circuits (e.g., FET currents, ring oscillator periods and NAND gate delay, or worst product of RC and worst R in an interconnect model) simultaneously.
In other words, a problem on skew corner is:
Given that the nominal and tolerance values of all model parameters in a compact device model have been determined, how to provide a fast skew model or a slow skew model in which there is no distribution for any compact model parameters. Specifically, how to set a model parameter's values so that the model will reproduce the fast or slow corner results of several circuits performance targets.